Methods ahd apparatus for removing parity bits frou binary words

ABSTRACT

1. IN A METHOD OF REMOVING WITH THE AID OF FIRST AND SECOND REGISTER MEANS, PARITY FROM BITS A FIRST CONTINUOUS STREAM OF BINARY WORDS INCLUDING DATA BITS AND SAID PARITY BITS AND BEING ACCOMPANIED BY A FIRST SERIES OF CLOCK PULSES, THE IMPROVEMENT COMPRISING IN COMBINATION THE STEPS OF: SHIFTING SAID FIRST STREAM OF BINARY WORDS INTO SAID FIRST REGISTER MEANS WITH SAID FIRST SERIES OF CLOCK PULSES, IDENTIFYING THE PARITY BITS IN THE FIRST STREAM OF BINARY WORDS, REMOVING THE IDENTIFIED PARITY BITS BY TRANSFERRING ONLY DATA BITS FROM SAID FIRST REGISTER MEANS TO SAID SECOND REGISTER MEANS, AND PROVIDING A SECOND CONTINUOUS STREAM OF BINARY WORDS IN WHICH (THE BINARY WORDS OF)DATA BITS FROM SAID FIRST STREAM ARE EXPANDED INTO THE TIME PERIODS OF THE REMOVED PARITY BITS, (AND) BY PROVIDING A SECOND SERIES OF CLOCK PULSES ADAPTED TO SAID EXPANDED (BINARY WORDS) DATA BITS IN THE SECOND STREAM AND BY SHIFTING SAID TRANSFERRED DATA BITS FROM SAID SECOND REGISTER MEANS WITH SAID SECOND SERIES OF CLOCK PULSES.

Nov. 26, 1974 METHODS AND Original Filed Aug. 4, 1972 W. H. SPENCER ETALAPPARATUS FOR azuovms man"! rm's FR on BINARY worms 7 Sheets-$heet 1 4%T Q9 4 7 49 Q- 1 a2 s :4 i 3. "2? gs I O (T T, T I 62 Q3 zfiWWVZ 27 m? 4J 9 r/53 {g /54 Nov. 26, 1974 w, s c ETAL Re. 28, Z57

IETEODS MID APPARATUS FOR REMOVING PARITY BITS PRO BINARY WORDS ori iiglFiled Aug. 4. 1972 7 Sheets-Sheet 2 coy/W52 Nov. 26, 1974 w. H. SPENCERRe. 28, Z57

IETHODS AND APPARATUS FOR REIOVING PARI'I'Y BITS PROI BINARY WORDSOrigihal Filed Aug. 4. 1972 7 Sheets-Sheet s Nov. 26, 1974 w. H. SPENCERETA!- Z57 IIE'I'EODS AND APPARATUS FOR REIOVIHG PARI'I'Y BITS rnollBINARY viunns Original Filed Aug. 4. 1972 '7 Sheets-Sheet 4 Nov. 26,1974 hETHODS AND APPARATUS FOR REIOVING PARI'I'Y BITS PRO" BINARY WO RDSori ini rned Au 4, 1972 7 Sheet-Sheet 5 w. H. SPENCER ETAL Re. 28 2'57IETHODS AID )JPARATUS FOR REIOVIHG PARI'I'Y BITS PRO BINARY W DRDS Nov.326, 1914 ori inal Filed Aug. 1., 1972 7 Sheets-Sheet 6 NOV. 26, 1974 w,SPENCER ETAL R0. 28, 251

IETHODS AND APPARATUS FOR REIOVING PARITY BITS PRO. BINARY WORDS UnitedStates Patent Oifice Re. 28,257 Reissued Nov. 26, 1974 28,257 METHODSAND APPARATUS FOR REMOVING PARITY BITS FROM BINARY WORDS William H.Spencer, Monrovia, and Brian K. Curtis, La Crescenta, Calif., assignorsto Bell & Howell Co., Chicago, Ill.

Original No. 3,764,998, dated Oct. 9, 1973, Ser. No. 278,137, Aug. 4,1972. Application for reissue Nov. 16, 1973, Ser. No. 416,712

Int. Cl. G06f 3/00, 5/06 US. Cl. 340-1725 22 Claims Matter enclosed inheavy brackets appears in the original patent but forms no part of thisreissue specification; mater printed in italics indicates the additionsmade by reissue.

ABSTRACT OF THE DISCLOSURE Methods and apparatus for removing paritybits from a first continuous stream of binary words accompanied by afirst series of clock pulses to identify the parity bits in the firststream of binary words and remove the identified parity bits. A secondcontinuous stream of binary words is provided in which the binary wordsof the first stream are expanded into the time period of the removedparity bits. A second series of clock pulses which is provided isadapted to the expanded binary words in the second stream.

There are also disclosed methods and apparatus for identifying paritybits in a continuous stream of binary words having 11 Word bits and pparity bits, the parity bits in different binary words being situated atcorresponding locations, and the number of binary one word and paritybits being odd in essentially each "word. These methods and apparatusdetermine for m(n+p) bits from the stream of binary words whether thenumber of binary one bits in each set of successive (n+p) bits of saidm(n+p) bits is even or odd, wherein m is a positive integer greater thanone. These methods and apparatus further identify the parity bits insaid m(n+p) bits on the basis of said corresponding locations inresponse to a determination that the number of binary one bits in eachset of successive (n+p) bits of said m(n+p) bits is odd.

CROSS-REFERENCE Methods and apparatus herein disclosed are compatiblewith methods and apparatus disclosed in the copending US. PatentApplication Ser. No. 278,138 filed of even date herewith by John L. Way,and Ser. No. 321,197, filed on Jan. 5, 1973 by John L. Way, as aContinuation in Part of said Serial No. 278,138, and being both assignedto the subject assignee. Subject matter herein disclosed is disclosedand/or claimed in said copending patent applications.

BACKGROUND OF THE INVENTION 1. Field of the Invention The subjectinvention relates to the field of pulse code modulation and, morespecifically, to methods and apparatus for removing parity bits fromstreams of binary words and to methods and apparatus for identifyingparity bits in streams of binary words.

2. Description of the Prior Art Known methods and apparatus are notsuitable for an identification or removal of parity bits from continuousstreams of binary words. Factors which contribute to this probleminclude the lack of an indication as to the start of each binary word inthe continuous stream and the identity of parity bits with data bits asfar as pulse shape is concerned.

SUMMARY OF THE INVENTION It is an object of this invention to overcomethe above mentioned disadvantages.

It is an object of this invention to provide methods and apparatus foridentifying parity bits in continuous streams of binary words.

It is an object of this invention to provide methods and apparatus forremoving parity bits from continuous streams of binary words.

Other objects of this invention will become apparent in the furthercourse of this disclosure.

From one aspect thereof, this invention resides in a method of removingwith the aid of first and second register means parity bits from a firstcontinuous stream of binary wonds including data bits and said paritybits and being accompanied by a first series of clock pulses. Theinvention according to this aspect resides, more specifically, in theimprovement comprising in combination the steps of shifting the firststream of binary words into the first register means with the firstseries of clock pulses, identifying the parity bits in the first streamof binary words, removing the identified parity bits by transferringonly data bits from the first register means to the second registermeans, and providing a second continuous stream of binary words in whichdata bits from [the binary words of] said first stream are expanded intothe time periods of the removed parity bits[, and] by providing a secondseries of clock pulses adapted to said expanded data bits [binary words]in the second stream and by shifting said transferred data bits fromsaid second register means with said second series of clock pulses.

[From another aspect thereof, the subject invention resides in a methodof identifying parity bits in a continuous stream of binary words havingit word bits and p parity bits, the parity bits in difierent binarywords being situated at corresponding locations, and the number ofbinary one word and parity bits being odd in essentially each Word. Theinvention according to this aspect resides, more specifically, in theimprovement comprising in combination the steps of determining form(n+p) bits from said stream of binary words whether the number ofbinary one bits in each set of successive (n+p) bits of said m(n+p) bitsis even or odd, wherein m is a positive integer greater than one; andidentifying the parity bits in said m(n+p) bits on the basis of saidcorresponding locations in response to a determination that the numberof binary one bits in each set of successive (n+ p) bits of said m(n+p)bits is odd] from another aspect thereof, the subject invention residesin apparatus for removing parity bits from a first continuous stream ofbinary words including data bits and said parity bits and beingaccompanied by a first series of clock pulses. The invention accordingto this aspect resides, more specifically, in the improvementcomprising, in combination, first means including first register meansand means connected to said first register medns for shifting binarywords from said first continuous stream including data bits and paritybits into said first register means, second means connected to saidfirst register medns for identifying parity bits in the first stream ofbinary words, [second] third means connected to the first means forremoving the identified parity bits, said third means including secondregister means connected to said first register means and meansconnected to said second register means for transferring only data bitsfrom said first register means to said second register means, [third]dnd fourth means for providing a second continuous stream of binarywords in which data bits from said third means including fourth meansfor expanding for said second stream the binary words of] said firststream are expanded into the time periods of the removed parity bits,said fourth means including [and] fifth means for providing a secondseries of clock pulses adapted to said expanded [binary words] data bitsin said second stream and means for shifting said transferred data bitsfrom said second register means with said second series of clock pulses.

[From another aspect thereof, the subject invention resides in anapparatus for identifying parity bits in a continuous stream of binarywords having n word bits and p parity bits, the parity bits in differentbinary words being situated at corresponding locations, and the numberof binary one word and parity bits being odd in essentially each word.The invention according to this aspect resides, more specifically, inthe improvement comprising, in conr bination, means for determining form(n+ bits from said stream of binary words whether the number of binaryone bits in each set of successive (n+p) bits of said ru(n+p) bits iseven or odd, wherein In is a positive integer greater than one, andmeans connected to said determining means for identifying the paritybits in said m(n+p) bits on the basis of said corresponding locations inresponse to a determination that the number of binary one bits in eachset of succesive (n-l-p) bits of said m(rz+p) bits is odd] BRIEFDESCRIPTION OF THE DRAWINGS of operation of the part of the apparatusshown in FIG. 4;

FIG. 7 is a representation of wave forms illustrating the operation ofthe system of FIGS. 1 to S; and

FIG. 8 is a diagram showing how the sheets containing FIGS. 1 to shouldbe positioned for a showing of the illustrated methods and apparatus.

DESCRIPTION OF PREFERRED EMBODIMENTS The preferred embodiment shown inFIGS. 1 to 5 has been designed for operation with NRZ codes. Thisnonretnrn to zero code is well known in the art. The chief advantage ofthis code is that its wave form does not return to zero between digitsof the same kind. This results in reduced bandwidth of the system andfacilitation of equipment. Those skilled in the art will recognize thatthese factors are not unique to NRZ codes. Accordingly, the utility ofthe subject invention is not confined t0 NRZ. codes. but extends toother codes in which an identification or removal of parity bits isnecessary or desirable.

Prolonged non-return to zero renders NRZ and similar codes not reliablyrecordable and reproducible. These and other reasons have prompted thedevelopment of a technique in which parity bits are inserted in binarycodes of the subject type so as to enhance binary transitions therein.

Particularly advantageous methods and apparatus for this purpose aredisclosed in the above mentioned copending Way application. In brief,Way discloses methods and apparatus for enhancing binary transitions ina first stream of binary words accompanied by a first series of clockpulses, each word having 11 bits and being accompanied by n clockpulses. Way, more specifically, discloses the improvement comprising incombination the steps of providing a second series of clock pulseshaving (n+1) clock pulses for each n clock pulses of the first series,providing a second stream of binary words in which each binary words ofthe first stream is accommodated within it clock pulses of the (n+1)clock pulses of the second series, and providing binary word in thesecond stream with parity bits during clock pulses outside the n clockpulses Within which each binary word is accommodated in the secondstream. A preferred example of the resulting wave form is shown at 10 inFIG. 7. As seen from the wave form 10, the binary words with parity bitsare in the form of a continuous stream of binary words. This raises theproblem of identifying the words in the absence of indications as to theword beginning or word ending as well as the problem of identifying theparity bits which are either binary zero bits or binary one hits justlike the data bits.

In general, each of the words 12, 13, 14 and of the first stream 10 ofbinary words has n word and p parity bits. In the illustrated example,there are seven word or data bits and one parity bit for each word. Ifthe number of binary one word or data bits in a word is odd, then theparity bit in that word is a binary zero. On the other hand, if thenumber of binary one word or data bits in a word is even, then theparity bit in that word is a binary one. In his manner, the number ofbinary one word and parity bits is odd in essentially each word. Thismaximizes an enhancement of binary transitions in the code.

The wave form 17 in FIG. 7 represents a first series of clock pulses.Whenever clock pulses are shown in FIG. 7, only the leading clock pulseedges are illustrated. In reality, the clock pulses typically havesignificant on-oif duty cycles, such as a duty cycle on the order of 50percent.

As seen in FIG. 7, each word 12, 13, 14 and 15 of the first stream 10 ofbinary words is accompanied by (n-l-p) clock pulses. Since the number ofclock pulses for each bit in the illustrated example is one, the firstseries of clock pulses 17 has eight clock pulses for each binary wordwith parity bit of the first stream 10 of binary words.

In accordance with the subject invention, a second continuous stream ofbinary words is provided in which the binary words of the first streamare expanded into the time period of the removed parity bits. Also, asecond series of clock pulses is provided which is adapted to theexpanded binary words in the second stream. In FIG. 7, the second seriesof clock pulses is illustrated by a wave form 1'9, and the second streamof binary Words is illustrated by a Wave form 20. In the illustratedpreferred embodiment, the second series of clock pulses 19 has 11 clockpulses for each (n+p) clock pulses of the first series 17. By way ofexample, the second series of clock pulses 19 has seven clock pulses foreach eight clock pulses of the first series 17. This may be viewed as anomission of the clock pulse which accompanied the parity bit in thefirst series.

As may be seen from the wave form in FIG. 7, the second stream of binarywords is not only characterized by an omission of the parity bits, butalso by an expansion of the binary words or data into the time periodsformerly occupied by the removed parity bits. Each Word 12, 13, 14' and15 of the second stream 20 of binary words thus extends over the timeinterval that Was in the first stream 10 occupied by the correspondingword and the accompanying parity bit. This has the great advantage thatthe streams of binary words are reconstituted into their original formin which there was no discontinuity between adjacent binary words.

Inventive methods and apparatus for realizing the accomplishmentsillustrated in FIG. 7 will now be described with the aid of FIGS. 1through 6.

The first stream 10 of binary words with parity bits and the firstseries of clock pulses 17 are provided by equipment shown in block formin FIG, 1. The equipment 25 may, for instance, include an NRZ [NTRZ]-encoder, a binary transition enhancer of the type disclosed in the abovementioned copending patent application by John L. Way, and means forstoring or otherwise processing the enhanced coded information. Wherethe storing or processing means would distort the clock and data pulses,as is typically the case in magnetic tape recording and playback,equipment including a conventional bit synchronizer may be employed forrestoring the data essentially to the form shown at in FIG. 7, as wellas for regenerating the clock pulse series 17. The equipment symbolizedby the block does not form part of the subject invention.

The first stream 10 of binary words with parity bits is applied througha systems input terminal 27 to a first shift register 28. The shiftregister 28 may be of a conventional type, such as the shift registertype SN74164, made by Texas Instruments Incorporated, of Dallas, Tex.,and described and shown, for instance, in Texas Instruments catalogCC-l, Section 9, pages l22l25.

The shift register 28 has (n+p) set-reset stages 31, 32, 33, 34, 35, 36,37 and 38, wherein n is the number of word or data bits in each word andp is the number of parity bits in each word, in the first stream 10 ofbinary r words received through the input 27. In the instant case, thereare seven data bits and one parity bit for each word, so that the numberof set-reset stages in the shift register 28 is eight.

The register 28 has a NAND element 41 for receiving the data from thesource 25 through the systems input 27. The output of the NAND elementis connected to the R-input of the first set-reset flip-flop element 31by way of a lead 42. Conversely, the output of the NAND element 41 isconnected by an inverter 43 to the S-input of the first set-resetflip-flop element 31.

To operate the shift register 28 the clock pulses received from thesource 25 by way of a systems input 44, lead 45 and shift register input46, are applied to the clock or CF inputs of the flip-flop elements 31to 38 through an inverter 47. These clock pulses belong to the firstseries of clock pulses 17 illustrated in FIG. 7. Actuation of the clearor CL inputs of the flip-flop elements 31 to 38 is not desired in thesubject application of the shift register 28 so that the general clearinput 48 of the shift register, to which the clear inputs of theelements 31 to 38 are connected by way of an inverter 49, is tied to thebinary one output of a NAND element 51, shown in FIG. 3. The output ofthe NAND element 51 is connected to the input 48 of the shift register28 by leads 53, 54 and 55.

The equipment under consideration includes two fur ther shift registers28' and 28" which are identical to the shift register 28 and have inputand output terminals which are identical to the input and outputterminals of the shift register 28. Accordingly, the same referencenumerals are used in FIG. 2 for the shift registers 28' and 28" as forthe shift register 28 in FIG. 1, except that prime and double-primemarks are employed to distinguish the inputs and outputs of the shiftregisters 28 and 28", respectively from the inputs and outputs of theshift register 28.

The shift register 28 shown in FIG. 1 has parallel ontputs 61, 62, 63,64, 65, 66, 67 and 68 at Which the shifted (n+p) or (n+1) bits of thefirst data stream 10 appear. The shift registers 28 and 28" havecorresponding parallel outputs as seen in FIG. 2.

The output 68 of the shift register 28 is connected by a lead 71 to theinput 27' of the shift register 28'. Similarly, the output 68 of theshift register 28 is connected by a lead 72 to the input 27" of theshift register 28".

In order to enable an identification of the parity bits, m(n+p) word andparity bits of the first data stream 10 are shifted into the registers28, 28 and 28" by the first series of clock pulses 17, wherein m is apositive integer greater than two, n is the number of word or data bitsin a word and p is the number of parity bits in each word of the firstdata stream 10. If each word has no more than one parity bit, then itmay be said that m(n+1) word and parity bits are shifted into the regis-6 ters 28, 28' and 28". It will also be observed that m is equal to 3 inthe illustrated embodiment, since there are three shift registers 28, 28and 28".

It is to be carefully noted at this juncture that it would be incorrectto say that in words or, more specifically, three words are shifted intothe registers, 28, 28 and 28". For this to be possible, it would benecessary that the first data stream 10 contain some identification ofthe word beginnings or/and endings. As can be seen from the wave form 10in FIG. 7, no such indications are present in the data stream receivedfrom the source 25. Moreover, the shape of the parity bits is identicalto the shape of the word or data bits.

Accordingly, the subject invention employs an ingenious system foridentifying the parity bits without any reliance on an identification ofthe word as such or their beginnings and endings.

The parity bit identification system according to the subject inventionincludes a determination for (n+p) or (n+1) bits from the first stream10 of binary words whether the number of binary[s] one bits in the (n+p)or (n+1) bits is even or odd. Referring to the preferred exampleillustrated by the wave form 10 in FIG. 7, it will be recalled that theparity bit was a binary zero whenever the number of binary one word ordata bits in the particular word was odd (see for instance the word 12in FIG. 7). Conversely, the parity [bit] bits is a binary one, wheneverthe number of binary one word or data bit in the particular word is even(see for instance the words 13, 14 and 15in FIG. 7)

In consequence, essentially each word in the first data stream 10 has anodd number of binary one word and parity bits. Moreover, in thepreferred system under consideration, the word or data bits are locatedat corresponding first locations, while the parity bits are located atcorresponding second locations, in the different words of the first datastream 10.

On the basis of these facts, [I have] it has been as certainedtheoretically and experimentally that an identification of the paritybits is possible with the aid of a continual determination whether thebinary one word and parity bits in each set of received (n+p) or (n+1)bits of the first binary stream 10 is odd or even. The accuracy of thisidentification increases as the number of determination is increased.Accordingly, [I] we prefer a odd/ even determination for m(n+p) bitsfrom the first stream 10 of binary words, wherein m is :1 positiveinteger greater than one, n is the number of binary word or data bits ineach word and p is the number of parity bits in each word. The latterdetermination is carried out by checking whether the number of binaryone hits in each set of successive (n+p) bits of said m(n+p) bits iseven or odd. In the illustrated case, the determination proceeds bychecking whether the number of binary one bits in each set of successive[(n-l-l] (n+1) bits of said m(n+ 1) bits is even or odd.

The odd/even determination is preferably effected simultaneously for atleast some sets of successive (n+p) or (n+1) bits of the m(n-|-1) bits.Preparatory to a parity bit searching operation, as well as afteraccomplishment of an operable search routine, the odd/even determinationmay be effected successively for at least some sets of the definedsuccessive bits.

In the illustrated preferred embodiment, the means for effecting therequisite odd/even determinations include three parity checkers 75, 7Sand 75" which have identical inputs and outputs. These parity checkerswhich are shown in FIGS. 1 and 2, may be of a conventional type, such asthe odd/even parity checker type SN74180 made by Texas InstrumentsIncorporated, and described and shown, for instance, in TexasInstruments catalog CC- 401, Section 9, pages 309-314.

As seen in FIG. 1, the parity checkers 75, 75 and 75" have a number ofExclusive NOR elements 77, two

7 Exclusive OR elements 78, an inverter 79, a number of AND elements 81and two NOR elements 82.

The parity checker 75 has eight inputs 83, 84, 85, 86, 87, 88, 89 and 90which are, respectively, connected to the Outputs 61, 62, 63, 64, 65,66, 67 and 68 of the shift register 28. Corresponding connections areprovided for the corresponding terminals of the parity checkers 75' and75" as seen in FIG. 2.

In accordance with conventional practice, each of the parity checkers75, 75 and 75" has an even input 92, 92' and 92", respectively. Theparity checkers 75, 75 and 75" further have an even output 94, 94' and94". The even output of a parity checker reaches a binary one value ifthe number of binary one bits applied to the inputs 83 to 90 or 83' to90 or 83 to 92" is even. The parity checkers 75 and 75" also have an oddoutput 95 and 95", respectively. The parity checker 75 also has an oddoutput which, however, is not shown since it is not utilized in theinstant application.

The odd output of a parity checker rises to a value of a binary one ifthe number of binary one bits applied to the inputs 83 to 90 or 83" to90" is odd.

The even input 92" is tied to a binary one potential which is suppliedby a NOR element 97 by way of leads 98 and 99. The NAND element 97 isshown in FIG. 4 and the lead 98 extends over FIGS. 2, 3 and 4.

The odd output 95" of the parity checker 75" is connected by a lead 101to the even input 9 of the parity checker 75'. The even output 94' isconnected by an inverter 102 and a lead 103 to the even input 92 of theparity checker 75. Accordingly, the even output 94 of the parity checker75 is high (i.e. is a binary one) when the number of binary one bits ineach set of successive (n+p) bits of the m(n+p) bits shifted into theregisters 28, 28 and 28" is even. In a similar vein, the even output 94of the parity checker 72" is high when the number of binary one bits ofthe (n+p) bits in the register 28" is even. Conversely, the odd output95" of the parity checker 75" is high if the number of binary one bitsof the (n+p) bits in the shift register 28" is odd.

Considering the nature of the first stream of binary words 10 withidentically shaped word and parity bits, it is statistically possiblethat the number of binary one word and parity bits in three adjacentsets of (n+p) or (n+1) bits is odd, even when the three sets are notthree words but when each set is constituted by fragments of adjacentwords. This statistical probability can be diminished by increasing theabove mentioned factor m and effecting the odd/even determination forall in sets simultaneously. In terms of equipment and operaationalcomplexity, there are of course practical limits as to the magnitude ofthe factor m.

To overcome these limitations [1] we have devised a system which willcontinuously effect and evaluate the odd/even determinations. Apreferred embodiment of this system is shown in FIGS. 4 and 6.

The means for controlling and evaluating the odd/ even determinationinclude, according to the illustrated preferred embodiment of theinvention, a binary counter 112 having m(n+p) counting states. Withrespect to the counter 112 in the illustrated preferred embodiment thefactor in is 4, n is 7 and p is 1. Accordingly, there are 32 countingstages.

In order to more fully illustrate the operation of the counter 112 withassociated equipment a table of various counting stages is presently setforth. In column 1 so-called present" states are illustrated relative tothe states shown in the subsequent columns. The first state zerotogether with the subsequent 31 states constitute the 32 statespreviously referred to.

In column 2 of the table states are illustrated which occur when thenumber of binary one word and parity bits is odd in each of the threesets of bits in the registers 28, 28 and 28". In that case, thedesignation P:l may be used to indicate that the number of binary onebits in each of the three sets of bits is odd. The designation P 1 isused to indicate that the number of binary one bits in the set of bitsstored in the register 28" is odd. Column 3 illustrates counting stageswhich occur when the number of binary one bits in the register 28" isodd (P 1) while either or both the shift registers 28 and 28' have aneven number of binary one bits (P 0). It will be noted that thedesignation P=0 is employed to indicate that any one or more of the setsof bits in the registers 28, 28' and 28" has an even number of binaryone word or parity bits. Column 4 illustrates counting states whichoccur when at least the set of bits in the register 28" has an evennumber of binary one bits.

TABLE Column 1 Column 2 Column 3 Column 4 Present P=1, P =1 P=0, P5=1P=0, P3=0 HJKLM HJKLM 111 KLM HJKLM In the table just set forth, thevarious states are numbered at the right-hand side of each column. Toeffect and control the various switching states, the apparatus shown inFIG. 4 includes in accordance with the illustrated preferred embodimentof the invention a number of AND elements 115 to 117 and a number ofNAND elements 119 to 140, all connected as shown in FIG. 4.

In particular, a lead 142 connects the output 94" of the parity checkerto an input of the AND element 116 in FIG. 4. A lead 143 connects theoutput of the parity checker 75" to an input of the AND element 115. Alead 146 shown in FIGS. 1, 2, 3 and 4 with branches 147, 148, 149 and151 connects the output 94 of the parity checker 75 to the AND element115, NAND element 125, NAND elements 129 and and NAND element 133 inFIG. 4. The output 94 of the parity checker 75 is also connected by alead 153 to an inverter 154 which, in turn, is connected by a lead 156shown in FIGS, 1, 2, 3 and 4 with branches 157, 158 and 159 to NANDelements 121, 122, 126, 127, 128, 131, 132 and 134.

The clear or CL inputs of the J-K flip-flop elements H, J, K, L and Mare tied by the lead 98 to the binary one ouput of the NAND element 97.The inverse of the first series of clock pulses 17 received from thesource 25 clocks the counter 112. To this end, the lead 45 extendingover FIGS. 1, 2 and 3 is connected to an inverter 161 shown in FIG. 3. Alead 162 connects the output of the inverter 161 to the clock or CFinputs of the J-K flip-flop elements H, J, K, L and M.

The states shown in the above mentioned Table are also illustrated inFIG. 6. As seen in FIG. 6, odd/even determinations as to the word in theshift register 28" (P or P is made after every set of m(n+p) or m(n +1)counting states. In the illustrated preferred embodiment, this placesthese determinations at counting states number 7, 15 and 23. Each timesuch a determination indicates that P =1 the counter 112 is set back tozero preparatory to the commencement of a new counting operation. On theother hand, if a determination shows that P =0 the counting operationcontinues into the next counting stages of the series m(n+p) At thecounting step number 23 a determination is again made whether P =1 or P=0. If P l, the counter 112 is reset to zero. If 1 :0, the counter 112is ad vanced to step number 24. After that step a determination whetherP=1 or P:0 is made with each step with respect to the output of theparity checker 75 shown in FIG. 1. It will be recalled that the outputof the parity checker can only be odd if the number of binary one bitsin each set of bits in the shift registers 28, 28 and 28" is odd. It maythus be said that in the case of counting steps 24 to 31, the odd/evendetermination is made simultaneously on all sets of the m(n+p) bits,wherein m is 3, n is 7 and p is l in the illustrated preferredembodiment. Every determination that P=l resets the counter 121 to thezero state. Every determination that P=0 advances the counter by onestep until the step number 31 is reached. At that stage, a determinationthat P=0 recycles the counter to step number 24 as shown in FIG. 6.

Upon resetting of the counter 121 to the zero state in response to adetermination that P =1 or P=1, a broadside transfer of binary bits iseffected from the shift register 28 shown in FIG. 2 to a paralle-inserial-out shift register 181 shown in FIG. 3. This broadside transferproceeds by way of a series of leads 182 which extend from the terminals62" to 68" of the shift register 28" in FIG. 2 to inputs of the register181 in FIG. 3. It will be noted that no lead proceeds from the terminal61" of the shift register 28" to the shift register 181. It will also benoted that the first input 184 of the register 181 of FIG. 3 isgrounded. This is an important feature of the preferred illustratedemobdiment in that an omission of the parity bits is thereby effected.In other words, the parity bit which is stored in the shift register 28"in the flip-flop element corresponding to the output terminal 61" is nottransferred to the shift register 181. That this non-transferred bit isindeed the parity bit follows from the fact that the parity bits in thedata stream illustrated in FIG. 7 are located a corresponding locationsin the words 12, 13, 14 and (e.g. at the end of each word in theillustrated example). The word or data bits, on the other hand, arelocated at corresponding different locations and only these word or databits are therefore transferred to the register 18] via the abovementioned leads 182.

The shift register 181 shown in FIG. 3 has a number of AND elements 186and a number of AND elements 187. The shift register 181 furtherincludes a number of NOR elements 188 which have their inputs connectedto the AND elements 186 and 187 and which drive set-reset flip-flopelements 189 as shown. Leads 191 and 192 connect the clear inputs of theflip-flop elements 189 to the binary one output of the NAND element 51.

A shift/load input 195 and inverters 196 and 197 are provided to switchthe register 181 for broadside transfer of data from the register 28" tothe register 181 by way of the leads 182 upon the receipt of a loadsignal at the input 195.

The register 181 is clocked by way of a clock input 198 and a NORelement 199 by clock pulses from the second series of clock pulses 19illustrated in FIG. 7. Since the parity bits are not transferred to theregister 181 and since this register is clocked by the second series ofclock pulses 19, there is provided at an output 200 of the register 181a second continuous stream of binary words, as illustrated at 20 in FIG.7, in which the binary words of the first stream 10 are expanded intothe time periods of the removed parity bits. In other Words, the streamof data bits of each word of the second stream 20 is expanded to occupythe time slots of the stream of data bits as well as the time slot ofthe now removed parity bit or bits of each corresponding word of thefirst stream 10 of the binary words.

The shift register 181 may be of a conventional type, such as theparallel-in serial-out shift register Type SN 74l66 made by TexasInstruments Incorporated, and described and shown, for instance, inTexas Instruments catalog CC-40l, Section 9, pages l34l4l.

It will be noted at this juncture that the words in the second stream 20are not necessarily in synchronism with ths corresponding words in thefirst stream 10 in the manner shown in FIG. 7. Rather, the words in thesecond stream 20 may be delayed relative to the words in the firststream 10 due to normal delays occurring in practice in the operation ofthe illustrated equipment.

The generation of the second series of clock pulses 1') for operation ofthe second shift register 181 will now be described with the aid ofFIGS. 2 and 5. In general, the second series of clock pulses is providedby generating with the aid of the first series of clock pulses a signalhaving a frequency equal to bn times the clock pulse rate of the firstseries, and by generating with the aid of that signal a series of clockpulses having a pulse rate equal to l/lb(n+l)], wherein b is a positivenumber. In the illustrated preferred embodiment, this positive number isequal to one. Accordingly, the second series of clock pulses 19 is inthe illustrated preferred embodiment provided by generating with the aidof the first series of clock pulses 17 a signal having a frequency equalto seven times the clock pulse rate in the first series 17, and bygenerating with the aid of that signal a series of clock pulses 19having a rate equal to one-eighth times the latter frequency.

The latter frequency of seven times the clock pulse rate in the series17 is in the illustrated preferred embodiment generated with the aid ofa phase detector 202 and amplifier stage 203 shown in FIG. 2, and avoltage controlled oscillator 204 shown in FIG. 5. This system is basedon the corresponding system disclosed in the above mentioned John Waypatent application.

A lead 206 is connected to the lead to apply pulses from the firstseries of clock pulses 17 to NAND elements 207 and 208 of the phasedetector 202. A seven counter 209 has its Q and [Q] Q outputs connectedby leads 210 and 211 to the NAND elements 207 and 208 of the phasedetector 202.

The output of the NAND element 207 is applied to the inverting input ofan operational amplifier 213 by way of an inverter 214 and a resistor215. The output of the NAND element 208 is applied by way of a resistor216 to the inverting input of the operational amplifier 213. A variableresistor 218 is connected by way of a resistor 219 to the invertinginput of the amplifier 213 and provides for a zero adjustment of thephase-lock loop formed by way of the leads 210 and 211.

The signal thus applied to the inverting input of the amplifier 213 isrepresentative of the frequency difference between the clock pulsesreceived by way of the lead 206 and the feedback pulses received throughthe leads 210 and 211.

A voltage divider 221 applied to the non-inverting input of theoperational amplifier 213 a voltage of, say, plus 2.3 volts. Similarly,the voltage applied to the inverting input of the amplifier 112 is alsoplus 2.3 volts when the phase detector 202 senses zero differencebetween the rate of the clock pulses received through the lead 206 andthe frequency of the signal received by way of the leads 210 and 211.

Moreover, the voltage appearing at the output 223 of the operationalamplifier 213 is also plus 2.3 volts when the voltages at the invertingand non-inverting inputs of the amplifier 213 are equal to plus 2.3volts. The operational amplifier 213 may be of a conventional type, suchas the well-known Type 715, made, for instance, by the FairchildSemiconductor Division under the description A715, and described andshown in the [Fiarchild] Faircliild Linear Integrated Circuits catalogof November 1971 on pages 41-44. The latter voltages are, of course,only given by way of example as those skilled III the art willappreciate.

The operational amplifier 213 has a feedback ClICIllt 224 including alowpass filter. A capacitor 225 in the feedback circuit has a pair ofoppositely poled diodes 226 and 227 connected in parallel thereto. Thediodes 226 and 227 form an amplitude limiter which prevents spuriouslocking-in by the voltage controlled oscillator 204 by confining itsoperating range.

The output of the operational amplifier 213 1n FIG. 2 is connected tothe input 231 of the voltage controlled oscillator 204 in FIG. by way ofa resistor 232 and a lead 233. The lead 233 extends from FIG. 2 to FIG.5 by way of FIGS. 3 and 4.

A variable voltage for adjustment of the frequency of the voltagecontrolled oscillator 204 is provided by a variable resistor 235connected by way of a fixed resistor 236 to the voltage controlledoscillator input 231. The voltage controlled oscillator 204 includesinverters 238 and .239 connected to the input 231 by way of resistors241 and 242. The output of the inverters 238 and 239 are, respectively,connected to the presetting input and the clearing input of a J-Kflip-flop element 243. The flip-flop element 243 has its J, K and CP(clock pulse) inputs grounded. The Q and [Q] U outputs of the flip-flopselements 243 are connected to the inverters 238 and 239 by way ofmverters 244 and 245, respectively.

In general terms, the voltage controlled oscillator 204 generates at itsoutput 247 a signal having a frequency I equal to bn times the clockpulse rate of the first series of clock pulses 17. In the illustratedpreferred embodiment, the voltage controlled oscillator 204 generates atits output 247 a signal having a frequency equal to seven times the rateof the clock pulses in the first series 17. To permit operation withdifferent clock pulse rates, further J-K flip-flop elements (not shown)with associated selector switch (not shown) may be provided for a clockpulse rate division of 2,4,8, etc.

The output of the voltage controlled oscillator 204 IS applied by way ofa lead 256 as clock pulses to three J-K flip-flop elements 257, 258 and259 of an eight counter 261. A lead 262 extending from FIG. 5 throughFIGS. 4 and 3 to FIG. 2 applies the output of the voltage controlledoscillator 204 for a division by seven to the seven counter 209 which,in turn, applies the divided signal by way of leads 210 and 211 to thephase detector 202.

Since the voltage controlled oscillator 204 in effect multiplies theclock rate of the series 17 by 7, and since the seven counter 209divides the multiplied frequency by seven, it follows that the frequencyof the signal applied by way of the leads 210 and 211 to the phasedetector 202 is normally equal to the pulse rate of the pulse series 17derived from the source in FIG. 1. The phase detector 202, amplifierstage 203, voltage controlled oscillator 204, seven counter 209, andleads 210 and 211 form a phase-lock loop which slaves the outputfrequency of the voltage controlled oscillator 204 to the input pulserate of the phase detector 202.

To perform its function, the eight counter 261 includes NAND elements265, 266 and 267 connected as shown in FIG. 5. A modifier 269 includinga further J-K llipflop element 271 is provided and connected to theeight counter 261 in order to synchronize the second clock pulse series19 with the first clock pulse series 17 as far as the beginning of eachbinary word is concerned.

The eight counter 261 and modifier 271 further include NAND elements 273to 278 connected as shown in FIG. 5. The eight counter 26-1 and modifier269 moreover include NAND elements 281 and 282. The NAND element 271 hasits input conected to the Q and [Q] outputs of the modifier flip-flopelement 271. The NAND element 282 has one input connected to the outputof the NAND element 281 and another input connected by way of a lead 284to the Q output of the fiip-fiop element 258 of the counter 261. Inconsequence, the clock pulses in the second series 19 are in synchronismwith the bits of the words in the second stream 20.

The resulting second clock pulse series 19 is applied by a lead 286,extending from FIG. 5 by way of FIG. 4 to FIG. 3, to the clock pulseinput 198 of the shift register 181. A terminal 287 is connected to theterminal 198 and lead 286 to provide at the data output terminal 200 anoutput terminal for the second series of clock pulses 19.

Generation of the load signal for the register 181 will now beconsidered in greater detail.

The counter 112 in FIG. 4 times the generation of the load signal forthe register 101 by way of three leads 291, 292 and 293 which,respectively, extend from the flip-flop elements K, L, and M in FIG. 4to a NAND element 296 in FIG. 5. The output of the NAND element 296 isconnected to the NAND elements 273 and 276, to the K- input of theflip-flop element 257 of the eight counter 261 and to an input of a NANDelement 301. The output of the NAND element 301 is connected to theJ-input of the flip-flop element 57, to an input of the NAND element265, to an input of a NAND element 302, and, by way of a lead 304 to theAND element 116 and to the NAND element 120, 122, and 127 in FIG. 4.

A lead 306 connects the [Q] Q output of the flip-flop element 258 of theeight counter 261 to the other input of the NAND element 302. The outputof the NAND element 302 in FIG. 5 is connected by a lead 308 to theshift/load input of the register 181 in FIG. 3. The lead 308 extends byway of FIG. 4 as shown.

In the operation of the illustrated equipment, the NAND element 302shown in FIG. 5 operates by way of the lead 308 to apply a load signalto the input 195 of the register 181 whenever a loading of data from theshift register 28" by way of the leads 182 into the shift register 181is to be effected. As previously indicated, the data thus transferred tothe shift register 181 are serially shifted out through the output 200under the control of the second series of clock pulses 19 applied to theinput terminal 198 of the shift register 181. In this manner, the datarepresented by the second stream of binary words 20 in FIG. 7 arerealized.

It will thus be recognized that the illustrated equipment meets all theobjectives of the subject invention defined initially and set forththroughout this disclosure.

Variations and modifications within the spirit and scope of the subjectinvention will suggest themselves from the subject disclosure to thoseskilled in the art.

We claim:

1. In a method of removing with the aid of first and second registermeans," parity from bits a first continuous stream of binary wordsincluding data bits and said parity bits and being accompanied by afirst series of clock pulses, the improvement comprising in combinationthe steps of:

shifting said first stream of binary words into said first registermeans with said first series of clock pulses; identifying the paritybits in the first stream of binary words;

removing the identified parity bits by transferring only data bits fromsaid first register means to said secand register means; and

providing a second continuous stream of binary words in which [thebinary words of] data bits from said first stream are expanded into thetime periods of the removed parity bits; [and] by providing a secondseries of clock pulses adapted to said expanded [binary words] data bitsin the second stream and by shifting said transferred data bits fromsaid second register means with said second series of clock pulses.

2. A method as claimed in claim 1, wherein:

each binary word in said first stream is provided with n bits;

each binary word in said first stream is accompanied by (n+p) clockpulses of said first series of clock pulses, wherein p is equal to thenumber of parity bits per binary word in said first stream;

said second series of clock pulses is provided with n clock pulses foreach (n-t-p) clock pulses of said first series of clock pulses; and

said second stream of binary words is provided by extending each binaryword of said first stream over it clock pulses of said second series ofclock pulses.

3. A method as claimed in claim 1, wherein:

each binary word in said first stream is provided with n word bits andwith no more than one parity bit, the parity bits in the differentbinary words being situated at corresponding locations;

each binary word with parity bit in said first stream is accompanied by(n+1) clock pulses of said first series of clock pulses;

said second series of clock pulses is provided with 11 clock pulses foreach (n+1) clock pulses of said first series of clock pulses; and

said second stream of binary words is provided by extending each binaryword of said first stream over n clock pulses of said second series ofclock pulses.

4. A method as claimed in claim 3, wherein:

said second series of clock pulses is synchronized with said firstseries of clock pulses.

5. A method as claimed in claim 3, wherein:

said second series of clock pulses is provided by generating with theaid of said first series of clock pulses a signal having a frequencyequal to bn times the clock pulse rate of said first series, and bygenerating with the aid of said signal a series of clock pulses having apulse rate equal to 1/[b(n+1)], wherein b is a positive number.

6. A method as claimed in claim 1, wherein:

each binary word in said first stream is provided with :1 word bits andp parity bits;

said identification of parity bits includes the step of determining for(n+p) bits from said first stream of binary words whether the number ofbinary one bits in said (n+p) bits is even or odd; and

said removal of identified parity bits includes the step of transferringfrom said first register means to said second register means only ithits of said (n+p) bits in response to said determination.

7. A method as claimed in claim 6, wherein:

said identification of parity bits includes the further step ofdetermining for m(n+p) bits from said first stream of binary wordswhether the number of hinary one bits in each set of successive (n-l-p)bits of said m(n+p) bits is even or odd, wherein m is a positive integergreater than one; and

said removal of identified parity bits includes the step of transferringin response to said determination only it hits from said first registermeans to said second register means from each set of successive (n-l-p)bits of said m(n+p) bits.

8. A method as claimed in claim 1, wherein:

each binary word in said first stream is provided with 11 word bits andp parity bits;

said identification of parity bits includes the step of determining form(n+p) bits from said first stream of binary words whether the number ofbinary one hits in each set of successive (n-|-p) bits of said m(n+p)bits is even or odd, wherein m is a positive integer greater than one;and

said removal of identified parity bits includes the step of transferringin response to said determination only 11 bits fr m said first registermeans to said second register means from each set of successive (n+1))bits of said m(n+p) bits.

9. A method as claimed in claim 1, wherein:

each binary word in said first stream is provided with 11 word bits andno more than one parity bit, the n word bits in different binary wordsbeing situated at corresponding first locations and the parity bits indifferent binary words being situated at corresponding second locations,and the number of hinary one word and parity bits being odd inessentially each word;

said identification of parity bits includes the step of determining for(n+1) bits from said first stream of binary words whether the number ofbinary one hits in said (n+1) bits is even or odd; and

said removal of identified parity bits includes the step of transferringfrom said first register means to said second register means only binarybits from said first locations in response to a determination that thenumber of binary one hits in said (n+1) bits is odd.

10. A method as claimed in claim 9, wherein:

said identification of parity bits includes the further step ofdetermining for m(n+l) bits from said first stream of binary wordswhether the number of binary one bits in each set of successive (n+1)bits of said m(n+l) bits is even or odd, wherein m is a positive integergreater than one; and

said removal of identified parity bits includes the step of transferringfrom said first register means to said second register means only binarybits from said first locations of each set of successive (n+1) bits ofsaid m(n+l) bits in response to a determination that the number ofbinary one hits in each set of successive (n+1) bits of said m(n+l) bitsis odd.

11. A method as claimed in claim 1, wherein:

each binary word in said first stream is provided with n word bits andno more than one parity bit, the 11 word bits in different binary wordsbeing situated at corresponding first locations and the parity bits indifferent binary words being situated at corresponding second locations,and the number of hinary one word and parity bits being odd inessentially each Word;

said identification of parity bits includes the step of determining form(n+l) bits from said first stream of binary words whether the number ofbinary one bits in each set of succesive (n+1) bits of said m(n+l) bitsis even or odd, wherein m is a positive integer greater than one; and

said removal of identified parity bits includes the step of transferringfrom said first register means to said second register means only binarybits from said first locations of each set of successive (n+1) bits ofsaid m(n+l) bits in response to a determination that the number ofbinary one hits in each set of succesive (n+1) bits of said m(n+l) bitsis odd.

[12. In a method of identifying parity bits in a continuous stream ofbinary words having it word bits and p parity bits, the parity bits indifferent binary words being situated at corresponding locations, andthe number of binary one word and parity bits being odd in essentiallyeach word, the improvement comprising in combination the steps of:

15 in each set of successive (n+p) bits of said m(n+p) bits is odd] [13.A method as claimed in claim 12, wherein: said determination is effectedfor m(n+p) bits at a time] 14. A method as claimed in claim 12, wherein:11:1;

said determination includes the step of determining for m(n+l) bits fromsaid stream of binary words whether the number of binary one hits ineach set of successive (n+1) bits of said m(n+l) bits is even or odd;and

said identification of parity bits includes the step of identifying theparity bits in said m(n+l) bits on the basis of said correspondinglocations in response to a determination that the number of binary onebits in each set of successive (n+1) bits of said m(n+l) bits is odd.]

[15. A method as claimed in claim 14, wherein:

said determination is effected for m(n+l) bits at a time] 16. Inapparatus for removing parity bits from a first continuous stream ofbinary words including data bits and said parity bits and beingaccompanied by a first series of clock pulses, the improvementcomprising in combination:

first means including first register means and means connected to saidfirst register means for shifting binary words from said firstcontinuous stream including data bits and parity bits into said firstregister means;

second means connected to said first register means for identifyingparity bits in the first stream of binary words;

[second] third means connected to the first means for removing theidentified parity bits, said third means including second register meansconnected to said first register means and means connected to saidsecond register means for transferring only data bits from said firstregister means to said second register means; and

[third] fourth means for providing a second continuous stream of binarywords said third means including fourth means for expanding for saidsecond stream] in which data bits from [the binary words of] said firststream are expanded into the time periods of the removed parity bitsand] said fourth means ineluding fifth means for providing a secondseries of clock pulses adapted to said expanded [binary words] data bitsin said second stream and means for shifting said transferred data bitsfrom said second register means with said second series of clock pulses.

17. An apparatus as claimed in claim 16, wherein:

said second register [third] means include a parallel-in serial-outshift register [and means for clocking said shift register]; and saidthird means include means connected between said first and secondregister means for transferring only data bits to parallel inputs ofsaid parallel-in-serial-out shift register [with said second series ofclock pulses].

18. An apparatus as claimed in claim 16, for removing parity bits from afirst continuous stream of binary words in which each Word has 11 bitsand is accompanied by (n+p) clock pulses of said first series of clockpulses, wherein p is equal to the number of parity bits per binary wordin said first stream, characterized in that:

said fifth means include means for providing said second series of clockpulses with n clock pulses for each (n+p) clock pulses of said firstseries of clock pulses; and

said fourth means include means for extending each binary word of saidfirst stream over 11 clock pulses of said second series of clock pulses.

19. An apparatus as claimed in claim 16, for removing parity bits from afirst continuous stream of binary words in which each word has n wordbits and no more than one parity bit, the parity bits in the difierentbinary words being situated at corresponding locations, and the firstseries of clock pulses having (n+1) clock pulses for each binary wordwith parity bit, characterized in that:

said fifth means include means for providing said second series of clockpulses with n clock pulses for each (n+1) clock pulses of said firstseries of clock pulses; and

said fourth means include means for extending each binary word of saidfirst stream over n clock pulses of said second series of clock pulses.

20. An apparatus as claimed in claim 19, wherein:

said fifth means include means for synchronizing said second series ofclock pulses with said first series of clock pulses.

21. An apparatus as claimed in claim 19, wherein:

said fifth means include sixth means for generating with the aid of saidfirst series of clock pulses a signal having a frequency equal to bntimes the clock pulse rate of said first series, and seventh means forgenerating with the aid of said signal a series of clock pulses having apulse rate equal to l/ [b(n+l) wherein b is a positive number.

22. An apparatus as claimed in claim 16, for removing parity bits from afirst continuous stream of binary Words in which each binary word has 11word bits and p parity bits, characterized in that:

said second [first] means include means for determining for m(n+p) bitsfrom the first stream of binary words whether the number of binary onebits in each set of successive (n+p) bits of said m(n+p) bits is even orodd, wherein m is a positive integer greater than one; and

said third [second] means include means for from said first registermeans to said second register means transferring in response to saiddetermination only it bits from each set of successive (n+p) bits ofsaid m(n+p) bits.

23. An apparatus as claimed in claim 22, wherein:

said second [first] means include means for effecting said determinationsuccessively for at least some sets of successive (n-i-p) bits of saidm(n+p) bits.

24. An apparatus as claimed in claim 22, wherein:

said second [first] means include means for effecting said determinationsimultaneously for at least some sets of successive (n+p) bits of saidm(n+p) bits.

25. An apparatus as claimed in claim 22, wherein:

said second [first] means include counting means having m(n+p) countingstates.

26. An apparatus as claimed in claim 16, for removing parity bits from afirst continuous stream of binary words in which each binary word has nword bits and no more than one parity bit, the n word bits in differentbinary words being situated at corresponding first locations and theparity bits in different binary words being situated at correspondingsecond locations, and the number of binary one word and parity bitsbeing odd in essentially each word, characterized in that:

said second [first] means include means for determining for m(n+l) bitsfrom said first stream of binary words whether the number of binary onebits in each set of successive (n+1) bits of said m(n+l) bits is even orodd, wherein m is a positive integer greater than one; and

said third [second] means include means for transferring from said firstregister means to said second register means only binary bits from saidfirst locations of each set of successive (n+1) bits of said m(n+l) bitsin response to a determination that the number of binary one hits ineach set of successive (n+1) bits of said m(n+l) bits is odd.

[27. In an apparatus for identifying parity bits in a continuous streamof binary words having 11 word bits and p parity bits, the parity bitsin different binary words being situated at corresponding locations, andthe number of binary one word and parity bits being odd in essentiallyeach word, the improvement comprising in combination:

means for determining for m(n+p) bits from said stream of binary wordswhether the number of binary one bits in each set of successive (n+p)bits of said m(n+p) bits is even or odd, wherein m is a positive integergreater than one; and

means connected to said determining means for identifying the paritybits in said m(n+p) bits on the basis of said corresponding locations inresponse to a determination that the number of binary one bits in eachset of successive (n+p) bits of said m(n+p) bits is odd] [28. Anapparatus as claimed in claim 27, wherein:

said determining means include means for effecting said determinationsuccessively for at least some sets of successive (n+p) bits of saidm(n+p) bits] [29. An apparatus as claimed in claim 27, wherein:

said determining means include means for effecting said determinationsimultaneously for at least some sets of successive (n+p) bits of saidm(n+p) bits] [30. An apparatus as claimed in claim 27, for identifyingparity bits in a continuous stream of binary words having n word bitsand no more than one parity bit, characterized in that:

said determining means include means for determining for m(n+l) bitsfrom the first stream of binary words 18 whether the number of binaryone bits in each set of successive (n+1) bits of said m(n+l) bits iseven or odd; and said identifying means include means for identifyingthe parity bits in said in (n+1) bits on the basis of said correspondinglocations in response to a determination that the number of binary onebits in each set of successive (n+1) bits of said m(n+l) bits is add][31. An apparatus as claimed in claim 27, wherein: said determiningmeans include counting means having m(n+p) counting stages] ReferencesCited The following references, cited by the Examiner, are of record inthe patented file of this patent or the original patent.

UNITED STATES PATENTS 3,310,626 3/1967 Cassidy 17850 3,310,780 3/1967Gilley et al. 340-1725 3,348,203 10/1967 Allen 340167 3,387,086 6/1968Beresin 178-50 3,413,611 11/1968 Fuetze 340172.5 3,548,309 12/1970Saltzberg et al. 325-38 3,576,396 4/1971 Sloate 17869.5 F 3,612,66010/1971 Miller 340172.5 3,652,803 3/1972 Joel, Jr. 17918 J 3,696,33810/1972 Preiss 340l72.5

GARETH D. SHAW, Primary Examiner J. D. THOMAS, Assistant Examiner US.Cl. X.R. 179BV

